Publications
2025
- "SSD Offloading for LLM Mixture-of-Experts Weights Considered Harmful in Energy Efficiency," K. Kyung, S. Yun, and J. Ahn, IEEE Computer Architecture Letters, 2025
- "Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads," J. Kim, S. Baek, M. Wi, H. Nam, M. J. Kim, S. Lee, K. Shon, and J. Ahn, IEEE Computer Architecture Letters, 2025
- "Cosmos: A CXL-Based Full In-Memory System for Approximate Nearest Neighbor Search," S. Ko, H. Shim, W. Doh, S. Yun, J. So, Y. Kwon, S.-S. Park, S.-D. Roh, M. Yoon, T. Song, and J. Ahn, IEEE Computer Architecture Letters, 2025
- "PET: Proactive Demotion for Efficient Tiered Memory Management," W. Doh*, Y. Moon*, S. Ko, S. Chung, K. Kyung, E. Lee, and J. Ahn, in Proceedings of the Twentieth European Conference on Computer Systems, 2025
* Joint First Authors
- "Marionette: A RowHammer Attack via Row Coupling," S. Baek, M. Wi, S. Park, H. Nam, M. J. Kim, N. Kim, and J. Ahn, in Proceedings of the 30th International Conference on Architectural Support for Programming Languages and Operating Systems, 2025
- "M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems," Y. Sun, J. Kim, Z. Yu, J. Zhang, S. Chai, M. J. Kim, H. Nam, J. Park, E. Na, Y. Yuan, R. Wang, J. Ahn, T. Xu, and N. Kim, in Proceedings of the 30th International Conference on Architectural Support for Programming Languages and Operating Systems, 2025
- "X-PPR: Post Package Repair for CXL Memory," C. Song, M. J. Kim, Y. Sun, H. Ji, K. Kim, T. Ko, and J. Ahn, IEEE Computer Architecture Letters, 2025
- "Anaheim: Architecture and Algorithms for Processing Fully Homomorphic Encryption in Memory," J. Kim, S. Yun, H. Ji, W. Choi, S. Kim, and J. Ahn, in Proceeding of 31th IEEE International Symposium on High Performance Computer Architecture, 2025
[CAL]
[CAL]
[CAL]
[EuroSys]
[ASPLOS]
[ASPLOS]
[CAL]
[HPCA]
2024
- "Hechi: A Hybrid Approach for Efficient Memory Reclamation Techniques in Mobile Systems," W. Doh, S. Ko, M. J. Kim, and J. Ahn, IEEE Embedded Systems Letters, 2024
- "NeuJeans: Private Neural Network Inference with Joint Optimization of Convolution and FHE Bootstrapping," J. Ju*, J. Park*, J. Kim, M. Kang, D. Kim, J. Cheon, and J. Ahn, Proceedings of the 2024 ACM SIGSAC Conference on Computer and Communications Security, 2024
* Joint First Authors
- "Duplex: A Device for Large Language Models with Mixture of Experts, Grouped Query Attention, and Continuous Batching," S. Yun, K. Kyung, J. Cho, J. Choi, J. Kim, B. Kim, S. Lee, K. Sohn, and J. Ahn, in Proceeding of the 57th annual IEEE/ACM International Symposium on Microarchitecture, 2024
- "Accelerating Programmable Bootstrapping Targeting Contemporary GPU Microarchitecture," H. Ji, S. Kim, J. Choi, and J. Ahn, IEEE Computer Architecture Letters, 2024
- "DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands," H. Nam, S. Baek, M. Wi, M. J. Kim, J. Park, C. Song, N. S. Kim, and J. Ahn, in Proceedings of the 51st Annual International Symposium on Computer Architecture, 2024
- "Native DRAM Cache: Re-architecting DRAM as a Large-Scale Cache for Data Centers," Y. Ryu, Y. Kim, G. Jung, J. Ahn, and J. Kim, in Proceedings of the 51st Annual International Symposium on Computer Architecture, 2024
- "IDT: Intelligent Data Placement for Multi-tiered Main Memory with Reinforcement Learning," J. Chang, W. Doh, Y. Moon, E. Lee, and J. Ahn, in Proceedings of the 33rd International Symposium on High-Performance Parallel and Distributed Computing, 2024
- "CLAY: CXL-based Scalable NDP Architecture Accelerating Embedding Layers," S. Yun, H. Nam, K. Kyung, J. Park, B. Kim, Y. Kwon, E. Lee, and J. Ahn, in Proceedings of the 38th ACM International Conference on Supercomputing, 2024
- "CiFHER: A Chiplet-Based FHE Accelerator with a Resizable Structure," S. Kim, J. Kim, J. Choi, and J. Ahn, International Symposium on Secure and Private Execution Environment Design, 2024
- "AttAcc! Unleashing the Power of PIM for Batched Transformer-based Generative Model Inference," J. Park*, J. Choi*, K. Kyung, M. J. Kim, Y. Kwon, N. S. Kim, and J. Ahn, in Proceedings of the 29th International Conference on Architectural Support for Programming Languages and Operating Systems, 2024
* Joint First Authors
- "TAROT: A CXL SmartNIC-Based Defense Against Multi-bit Errors by Row-Hammer Attacks," C. Song, M. J. Kim, T. Wang, H. Ji, J. Huang, I. Jeong, J. Park, H. Nam, M. Wi, J. Ahn, and N. S. Kim, in Proceedings of the 29th International Conference on Architectural Support for Programming Languages and Operating Systems, 2024
- "An LPDDR-based CXL-PNM Platform for TCO-efficient Inference of Transformer-based Large Language Models," S.-S. Park, K. Kim, J. So, J. Jung, J. Lee, K. Woo, N. Kim, Y. Lee, H. Kim, Y. Kwon, J. Kim, J. Lee, Y. Cho, Y. Tai, J. Cho, H. S, J. Ahn, and N. S. Kim, in Proceeding of 30th IEEE International Symposium on High Performance Computer Architecture, 2024
- "HyPHEN: A Hybrid Packing Method and Its Optimizations for Homomorphic Encryption-Based Neural Networks," D. Kim*, J. Park*, J. Kim, S. Kim, and J. Ahn, IEEE Access, Vol. 12, 2024
* Joint First Authors
[ESL]
[CCS]
[MICRO]
[CAL]
[ISCA]
[ISCA]
[HPDC]
[ICS]
[SEED]
[ASPLOS]
[ASPLOS]
[HPCA]
[Access]
2023
- "A Hardware-Friendly Tiled Singular-Value Decomposition-Based Matrix Multiplication for Transformer-Based Models," H. Li, J. Choi, Y. Kwon, and J. Ahn, IEEE Computer Architecture Letters, Vol. 22, No. 2, 2023
- "How to Kill the Second Bird with One ECC: The Pursuit of Row Hammer Resilient DRAM," M. J. Kim, M. Wi, J. Park, S. Ko, J. Choi, H. Nam, N. S. Kim, J. Ahn, E. Lee, in Proceeding of the 56th annual IEEE/ACM International Symposium on Microarchitecture, 2023
- "Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices," Y. Sun, Y. Yuan, Z. Yu, R. Kuper, C. Song, J. Huang, H. Ji, S. Agarwal, J. Lou, I. Jeong, R. Wang, J. Ahn, T. Xu, N. S. Kim, in Proceeding of the 56th annual IEEE/ACM International Symposium on Microarchitecture, 2023
- "Unleashing the Potential of PIM: Accelerating Large Batched Inference of Transformer-Based Generative Models," J. Choi, J. Park, K. Kyung, N. S. Kim, and J. Ahn, IEEE Computer Architecture Letters, Vol. 22, No. 2, 2023
- "X-ray: Discovering DRAM Internal Structure and Error Characteristics by Issuing Memory Commands," H. Nam, S. Baek, M. Wi, M. J. Kim, J. Park, C. Song, N. S. Kim, and J. Ahn, IEEE Computer Architecture Letters, Vol. 22, No. 2, 2023
- "GraNDe: Efficient Near-Data Processing Architecture for Graph Neural Networks," S. Yun, H. Nam, J. Park, B. Kim, J. Ahn, and E. Lee, IEEE Transactions on Computers, Vol. 73, No. 10, 2023
- "SHARP: A Short-Word Hierarchical Accelerator for Robust and Practical Fully Homomorphic Encryption," J. Kim, S. Kim, J. Choi, J. Park, D. Kim, and J. Ahn, in Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
- "ADT: Aggressive Demotion and Promotion for Tiered Memory," Y. Moon, W. Doh, K. Kyung, E. Lee, and J. Ahn, IEEE Computer Architecture Letters, Vol. 22, No. 1, 2023
- "SHADOW: Preventing Row Hammer in DRAM with Intra-Subarray Row Shuffling," M. Wi*, J. Park*, S. Ko, M. J. Kim, N. S. Kim, E. Lee, and J. Ahn, in Proceeding of 29th IEEE International Symposium on High Performance Computer Architecture, 2023
* Joint First Authors
[CAL]
[MICRO]
[MICRO]
[CAL]
[CAL]
[TC]
[ISCA]
[CAL]
[HPCA]
Previous
- [IISWC]
- "Accelerating Transformer Networks through Recomposing Softmax Layers," J. Choi, H. Li, B. Kim, S. Hwang, and J. Ahn, IEEE International Symposium on Workload Characterization, 2022
- "A Slice and Dice Approach to Accelerate Compound Sparse Attention on GPU," H. Li, J. Choi, and J. Ahn, IEEE International Symposium on Workload Characterization, 2022
- "Future Scaling of Memory Hierarchy for Tensor Cores and Eliminating Redundant Shared Memory Traffic Using Inter-Warp Multicasting," S. Lee, S. Hwang, M. J. Kim, J. Choi, and J. Ahn, IEEE Transactions on Computers, Vol. 71, No. 12,, 2022
- "ARK: Fully Homomorphic Encryption Accelerator with Runtime Data Generation and Inter-Operation Key Reuse," J. Kim*, G. Lee*, S. Kim, G. Sohn, M. Rhu, J. Kim, and J. Ahn, in Proceeding of the 55th annual IEEE/ACM International Symposium on Microarchitecture, 2022
* Joint First Authors
- "GraNDe: Near-Data Processing Architecture with Adaptive Matrix Mapping for Graph Convolutional Networks," S. Yun, B. Kim, J. Park, H. Nam, J. Ahn, and E. Lee, IEEE Computer Architecture Letters, Vol. 21, No. 2, 2022
- "BTS: An Accelerator for Bootstrappable Fully Homomorphic Encryption," S. Kim, J. Kim, M. J. Kim, W. Jung, J. Kim, M. Rhu, and J. Ahn, in Proceedings of the 49th International Symposium on Computer Architecture, 2022
- "MaPHeA: A Framework for Lightweight Memory Hierarchy-Aware Profile-Guided Heap Allocation," D. Oh, Y. Moon, D. K. Ham, T. J. Ham, Y. Park, J. W. Lee, J. Ahn, and E. Lee, ACM Transactions on Embedded Computing Systems, 2022
- "MVP: An Efficient CNN Accelerator with Matrix, Vector, and Processing-Near-Memory Units," S. Lee, J. Choi, W. Jung, B. Kim, J. Park, H. Kim, and J. Ahn, ACM Transactions on Design Automation of Electronic Systems, 2022
- "Mithril: Cooperative Row Hammer Protection on Commodity DRAM Leveraging Managed Refresh," M. J. Kim, J. Park, Y. Park, W. Doh, N. Kim, T. J. Ham, J. W. Lee, and J. Ahn, in Proceeding of 28th IEEE International Symposium on High Performance Computer Architecture, 2022
- "TRiM: Enhancing Processor-Memory Interfaces with Scalable Tensor Reduction in Memory," J. Park*, B. Kim*, S. Yun, E. Lee, M. Rhu, and J. Ahn, in Proceeding of the 54th annual IEEE/ACM International Symposium on Microarchitecture, 2021
* Joint First Authors
- "Over 100x Faster Bootstrapping in Fully Homomorphic Encryption through Memory-centric Optimization with GPUs," W. Jung, S. Kim, J. Ahn, J. H. Cheon, and Y. Lee, IACR Transactions on Cryptographic Hardware and Embedded Systems, 2021
- "Accelerating Fully Homomorphic Encryption Through Architecture-Centric Analysis and Optimization," W. Jung, E. Lee, S. Kim, J. Kim, N. Kim, K. Lee, C. Min, J. H. Cheon, and J. Ahn, IEEE Access, Vol. 9, 2021
- "MaPHeA: A Lightweight Memory Hierarchy-Aware Profile-Guided Heap Allocation Framework," D. Oh, Y. Moon, E. Lee, T. J. Ham, Y. Park, J. W. Lee, and J. Ahn, in Proceedings of the 22nd ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, 2021
- "BCD Deduplication: Effective Memory Compression Using Partial Cache-Line Deduplication," S. Park, I. Kang, Y. Moon, J. Ahn, and G. E. Suh, in Proceedings of the 26th International Conference on Architectural Support for Programming Languages and Operating Systems, 2021
- "Row-Streaming Dataflow Using a Chaining Buffer and Systolic Array+ Structure," H. Kim, S. Lee, J. Choi, and J. Ahn, IEEE Computer Architecture Letters, Vol. 20, No. 1, 2021
- "TRiM: Tensor Reduction in Memory," B. Kim, J. Park, E. Lee, M. Rhu, and J. Ahn, IEEE Computer Architecture Letters, Vol. 20, No. 1, 2021
- "Graphene: Strong yet Lightweight Row Hammer Protection," Y. Park, W. Kwon, E. Lee, T. J. Ham, J. Ahn, and J. W. Lee, in Proceeding of the 53rd annual IEEE/ACM International Symposium on Microarchitecture, 2020
- "Accelerating Number Theoretic Transformations for Bootstrappable Homomorphic Encryption on GPUs," S. Kim, W. Jung, J. Park, and J. Ahn, IEEE International Symposium on Workload Characterization, 2020
- "MViD: Sparse Matrix-Vector Multiplication in Mobile DRAM for Accelerating Recurrent Neural Networks," B. Kim, J. Chung, E. Lee, W. Jung, S. Lee, J. Choi, J. Park, M. Wi, S. Lee, and J. Ahn, IEEE Transactions on Computers, Vol. 69, No. 7, 2020
- "Comparing BERT and XLNet from the Perspective of Computational Characteristics," H. Li, J. Choi, S. Lee, and J. Ahn, 19th International Conference on Electronics, Information, and Communication, 2020
- "CAT-TWO: Counter-based Adaptive Tree, Time Window Optimized for DRAM Row-hammer Prevention," I. Kang, E. Lee, and J. Ahn, IEEE Access, Vol. 8, 2020
- "Enforcing Last-level Cache Partitioning through Memory Virtual Channels," J. Chung, Y. Ro, J. Kim, J. Ahn, J. Kim, J. Kim, J. W. Lee, and J. Ahn, in Proceeding of the 2019 International Conference on Parallel Architectures and Compilation Techniques, 2019
- "TWiCe: Preventing Row-hammering by Exploiting Time Window Counters," E. Lee, I. Kang, S. Lee, G. E. Suh, and J. Ahn, in Proceedings of the 46th International Symposium on Computer Architecture, 2019
- "Restructuring Batch Normalization to Accelerate CNN Training," W. Jung*, D. Jung*, B. Kim, S. Lee, W. Rhee, and J. Ahn, The Conference on Systems and Machine Learning, 2019
* Joint First Authors
- "Evaluating the Impact of Optical Interconnects on a Multi-Chip Machine-Learning Architecture," Y. Ro, E. Lee, and J. Ahn, MDPI Electronics, Vol. 7, No. 8, 2018
- "3D-XPath: High-Density Managed DRAM Architecture with Cost-effective Alternative Paths for Memory Transactions," S. Lee, K. Lee, M. Sung, M. Alian, C. Kim, W. Cho, R. Oh, S. O, J. Ahn, and N. S. Kim, in Proceeding of the 2018 International Conference on Parallel Architectures and Compilation Techniques, 2018
- "Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices," S. Lee, H. Cho, Y. H. Son, Y. Ro, N. S. Kim, and J. Ahn, IEEE Access, Vol. 6, 2018
- "Memory Hierarchy for Web Search," G. Ayers, J. Ahn, C. Kozyrakis, and P. Ranganathan, in Proceeding of 24th IEEE International Symposium on High Performance Computer Architecture, 2018
- "TWiCe: Time Window Counter Based Row Refresh to Prevent Row-hammering," E. Lee, S. Lee, G. E. Suh, and J. Ahn, IEEE Computer Architecture Letters, Vol. 17, No. 1, 2018
- "Partitioning Compute Units in CNN Acceleration for Statistical Memory Traffic Shaping," D. Jung, S. Lee, W. Rhee, and J. Ahn, IEEE Computer Architecture Letters, Vol. 17, No. 1, 2018
- "Work as a Team or Individual: Characterizing System-level Impacts of Main Memory Partitioning," E. Lee, J. Chung, D. Jung, S. Lee, S. Li, and J. Ahn, IEEE International Symposium on Workload Characterization, 2017
- "SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture," Y. H. Son, H. Cho, Y. Ro, J. W. Lee, and J. Ahn, IEEE Computer Architecture Letters, Vol. 16, No. 1, 2017
- "Evaluation of Performance Unfairness in NUMA System Architecture," W. Son, H. Jung, J. Ahn, J. W. Lee, and J. Kim, IEEE Computer Architecture Letters, Vol. 16, No. 1, 2017
- "Excavating the Hidden Parallelism Inside DRAM Architectures with Buffered Compares," J. Lee, J. Chung, J. Ahn, and K. Choi, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 6, 2017
- "Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems," Y. Ro, M. Sung, Y. Park, and J. Ahn, IEICE Electronics Express, Vol. 14, No. 11, 2017
- "History-Based Arbitration for Fairness in Processor-Interconnect of NUMA Servers," W. Song, G. Kim, H Jung, J. Chung, J. Ahn, J. W. Lee, and J. Kim, in Proceedings of the 22nd International Conference on Architectural Support for Programming Languages and Operating Systems, 2017
- "SOUP-N-SALAD: Allocation-oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures," Y. Ro, H. Cho, E. Lee, D. Jung, Y. H. Son, J. Ahn, and J. W. Lee, in Proceeding of 23rd IEEE International Symposium on High Performance Computer Architecture, 2017
- "Defect Analysis and Cost-effective Resilience Architecture for Future DRAM Devices," S. Cha, S. O, H. Shin, S. Hwang, K. Park, S. Jang, J. Choi, G. Jin, Y. H. Son, H. Cho, J. Ahn, and N. S. Kim, in Proceeding of 23rd IEEE International Symposium on High Performance Computer Architecture, 2017
- "Chameleon: Versatile and Practical Near-DRAM Acceleration Architecture for Large Memory Systems," H. Asghari-Moghaddam, Y. H. Son, J. Ahn, and N. S. Kim, in Proceeding of the 49th annual IEEE/ACM International Symposium on Microarchitecture, 2016
- "Adaptive and Flexible Key-Value Stores Through Soft Data Partitioning," B. Hong, K. Kwon, J. Ahn, and J. Kim, in Proceeding of the 34th IEEE International Conference on Computer Design, 2016
- "Accelerating Linked-list Traversal Through Near-Data Processing," B. Hong, G. Kim, J. Ahn, Y. Kwon, H. Kim, and J. Kim, in Proceeding of the 2016 International Conference on Parallel Architectures and Compilation Techniques, 2016
- "Buffered Compares: Excavating the Hidden Parallelism Inside DRAM Architectures with Lightweight Logic," J. Lee, J. Ahn, and K. Choi, in Proceeding of the Design, Automation & Test in Europe, 2016
- "Large Pages on Steroids: Small Ideas to Accelerate Big Memory Applications," D. Jung, S. Li, and J. Ahn, IEEE Computer Architecture Letters, Vol. 15, No. 2, 2016
- "Exploring new features of high-bandwidth memory for GPUs," B. Li, C. Song, J. Wei, J. Ahn, and N. S. Kim, IEICE Electronics Express, Vol. 13, No. 14, 2016
- "Achieving One Bilion Key-Value Requests per Second on a Single Server," S. Li, H. LIm, V. W. Lee, J. Ahn, A. Kalia, M. Kaminsky, D. G. Andersen, S. O, S. Lee, and P. Dubey, IEEE Micro Top Picks, Vol. 36, No. 3, 2016
- "Full-Stack Architecting to Achieve a Billion-Requests-Per-Second Throughput on a Single Key-Value Store Server Platform," S. Li, H. Lim, V. W. Lee, J. Ahn, A. Kalia, M. Kaminsky, D. G. Andersen, S. O, S. Lee, and P. Dubey, ACM Transactions on Computer Systems, Vol. 34, No.2, 2016
- "Near-DRAM Acceleration with Single-ISA Heterogeneous Processing in Standard Memory Modules," H. Asgharimoghaddam, A. Farmahini-Farahani, K. Morrow, J. Ahn, N. S. Kim, IEEE Micro, Vol. 36, No. 1, 2016
- "A Study in Identifying Memory Address Interleaving of x86 Servers," J. Choi, D. Jung, and J. Ahn, in Proceedings of the 30th International Technical Conference on Circuits/Systems, Computers and Communications, 2015
- "Architecting to Achieve a Billion Requests Per Second Throughput on a Single Key-Value Store Server Platform," S. Li, H. Lim, V. W. Lee, J. Ahn, A. Kalia, M. Kaminsky, D. G. Andersen, S. O, S. Lee, and P. Dubey, in Proceedings of the 42nd International Symposium on Computer Architecture, 2015
- "History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures," K. Chen, S. Li, J. Ahn, N. Muralimanohar, J. Zhao, C. Xu, S. O, Y. Xie, J. B. Brockman, and N. P. Jouppi, in Proceedings of the 29th ACM on International Conference of Supercomputing, 2015
- "CiDRA: A Cache-inspired DRAM Resilience Architecture," Y. H. Son, S. Lee, S. O, S. Kwon, N. S. Kim, and J. Ahn, in Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
- "Alloy: Parallel-Serial Memory Channel Architecture for Single-Chip Heterogeneous Processor Systems," H.Wang, C.-J. Park, G.-S. Byun, J. Ahn, and N. S. Kim, in Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
- "NDA: Near-DRAM Acceleration Architecture Leveraging Commodity DRAM Devices and Standard Memory Modules," A. Farmahini-Farahani, J. Ahn, K. Morrow, and N. S. Kim, in Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
- "Reset-in-set: improving PCM write throughput by reducing the peak power of multi-bit writes," Y. Ro, E. Lee, and J. Ahn, Electronics Letters, Vol. 51, No. 17, 2015
- "CIDR: A Cache Inspired Area-Efficient DRAM Resilience Architecture against Permanent Faults," S. O, S. Kwon, Y. H. Son, Y. Park, and J. Ahn, IEEE Computer Architecture Letters, Vol. 14, No. 01, 2015
- "DRAMA: An Architecture for Accelerated Processing near Memory," A. Farmahini-Farahani, J. Ahn, K. Morrow, and N. S. Kim, IEEE Computer Architecture Letters, Vol. 14, No. 01, 2015
- "Memory Network: Enabling Technology for Scalable Near-Data Computing," K. S. Kim, J. Kim, J. Ahn, Y. K. Kwon, in Proceedings of the 2nd Workshop on Near-Data Processing in conjunction with the MICRO-47, 2014
- "Understanding DDR4 in Pursuit of In-DRAM ECC," S. H. Kwon, Y. H. Son, J. Ahn, in Proceedings of the 11th International SoC Design Conference, 2014
- "Microbank: Architecting Through-Silicon Interposer-Based Main Memory Systems," Y. H. Son, S. O, H. Yang, D. Jung, J. Ahn, J. Kim, J. Kim, and J. W. Lee, in Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, 2014
- "Row-Buffer Decoupling: A Case for Low-Latency DRAM Microarchitecture," S. O, Y. H. Son, N. S. Kim, and J. Ahn, in Proceedings of the 41st International Symposium on Computer Architecture, 2014
- "Dynamic Bandwidth Scaling for Embedded DSPs with 3D-Stacked DRAM and Wide I/Os," D. W. Chang, Y. H. Son, J. Ahn, H. Kim, M. Ahn, M. J. Schulte, and N. S. Kim, in Proceedings of the 2013 International Conference on Computer-Aided Design, 2013
- "Memory-centric System Interconnect Design with Hybrid Memory Cubes," G. Kim, J. Kim, J. Ahn, and J. Kim, in Proceedings of the 22nd International Conference on Parallel Architecture and Compilation Techniques, 2013
- "Reducing Memory Access Latency with Asymmetric DRAM Bank Organizations," Y. H. Son, S. O, Y. Ro, J. W. Lee and J. Ahn, in Proceedings of the 40th International Symposium on Computer, 2013
- "McSimA+: A Manycore Simulator with Application-level+ Simulation and Detailed Microarchitecture Modeling," J. Ahn, S. Li, S. O and N. P. Jouppi, in Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2013
- "Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint," J. Lee, M. Chung, Y. Cho, S. Ryu, J. Ahn, and K. Choi, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 11, 2013
- "Exploiting Replicated Cache Blocks to Reduce L2 Cache Leakage in CMPs," H. Kim, J. Ahn, and J. Kim, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 10, 2013
- "Scalable High-Radix Router Microarchitecture Using a Network Switch Organization," J. Ahn, Y. H. Son, and J. Kim, ACM Transactions on Architecture and Code Optimization, Vol. 10, No. 3, 2013
- "MAEPER: Matching Access and Error Patterns With Error-Free Resource for Low Vcc L1 Cache," Y. Choi, S. Yoo, S. Lee, J. Ahn, and K. Lee, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 6, 2013
- "The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing," S. Li, J. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi, ACM Transactions on Architecture and Code Optimization, Vol. 10, No. 1, 2013
- "Chapter 5. The Role of Photonics in Future Datacenter Networks," A. Davis, N. P. Jouppi, M. McLaren, N. Muralimanohar, R. S. Schreiber, N. Binkert, and J. Ahn, in Optical Interconnects for Future Data Center Networks, Springer, 2013
- "A Memory Behavior Analysis Tool and Its Applications for Mobile Systems Exploiting Full-System Emulation," D. Lee, S. Lee, Y. H. Son, and J. Ahn, Journal of KIISE : Computer Systems and Theory, Vol.40, No.2, pp.77-87, 2013
- "MAGE - Adaptive Granularity and ECC for Resilient and Power Efficient Memory System," S. Li, D. H. Yoon, K. Chen, J. Zhao, J. Ahn, J. B. Brockman, Y. Xie, and N. P. Jouppi, in Proceedings of the International Conference for High Performance Computing, Networking, 2012
- "CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory," K. Chen, S. Li, J. Ahn, J. B. Brockman, and N. P. Jouppi, in Proceedings of the Design, Automation & Test in Europe, 2012
- "Network within a Network Approach to Create a Scalable High-Radix Router Microarchitecture," J. Ahn, S. Choo, and J. Kim, in Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012
- "Analyzing the Memory Access Behavior of a Booting Process Utilizing a Fast Full-System Analysis Tool," D. Lee, S. O, S. Lee, and J. Ahn, in Proceedings of the 2012 International Conference on Electronics, Information and Communication, 2012
- "ccTSA: A Coverage-Centric Threaded Sequence Assembler," J. Ahn, Public Library of Science (PLoS) ONE, Vol. 7, No. 6, 2012
- "Optical High-Radix Switch Design," N. Binkert, A. Davis, N. P. Jouppi, M. McLaren, N. Muralimanohar, R. S. Scheriber, and J. Ahn, IEEE Micro, Vol. 32, No.3, 2012
- "Improving System Energy Efficiency with Memory Rank Subsetting," J. Ahn, N. P. Jouppi, C. Kozyrakis, J. Leverich, and R. S. Schreiber, ACM Transactions on Architecture and Code Optimization, Vol. 9, No. 1, 2012
- "CACTI-P: Architecture-level Modeling for SRAM-based Structures with Advanced Leakage Reduction Techniques," S. Li, K. Chen, J. Ahn, J. B. Brockman, and N. P. Jouppi, in Proceedings of the 2011 International Conference on Computer-Aided Design, 2011
- "Exploring Energy-Efficient DRAM Array Organizations," S. O, S. Choo, and J. Ahn, in Proceedings of the 54th IEEE International Midwest Symposium on Circuits and Systems, 2011
- "The Role of Optics in Future High Radix Switch Design," N. Binkert, A. Davis, N. P. Jouppi, M. McLaren, N. Muralimanohar, R. Schreiber, and J. Ahn, in Proceedings of the 38th Annual International Symposium on Computer Architecture, 2011
- "Matching Cache Access Behavior and Bit Error Pattern for High Performance Low Vcc L1 Cache," Y. G. Choi, S. Yoo, S. Lee, and J. Ahn, in Proceedings of the Design Automation Conference, 2011
- "Chapter 4. Energy-Awareness on Contemporary Memory Systems," J. Ahn, S. Choo, and S. O, in Energy-Aware System Design: Algorithms and Architectures, 2011
- "Replication-Aware Leakage Management in Chip Multiprocessors with Private L2 Caches," H. Kim, J. Ahn, and J. Kim,, in Proceedings of the International Symposium on Low Power Electronics and Design, 2010
- "Chapter 14. Memory Modeling with CACTI," N. Muralimanohar, J. Ahn, and N. P. Jouppi, in Processor and System-on-Chip Simulation, 2010
- "Chapter 9. CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study," J Ahn, R. G. Beausoleil, N. Binkert, A. Davis, M. Fiorentino, N. P. Jouppi, M. McLaren, M. Monchiero, N. Muralimanohar, R. S. Schreiber, and D. Vantrease, in Low Power Networks-on-Chip,, 2010
- "McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures," S. Li, J. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi, in Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture, 2009
- "Future Scaling of Processor-Memory Interfaces," J. Ahn, N. P. Jouppi, C. Kozyrakis, J. Leverich, and R. S. Schreiber, in Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, 2009
- "HyperX: Topology, Routing, and Packaging of Efficient Large-Scale Networks," J. Ahn, N Binkert, A. Davis, M. McLaren, and R. S. Schreiber, in Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, 2009
- "Devices and architectures for photonic chip-scale integration," J. Ahn, M. Fiorentino, R. G. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. P. Jouppi, M. McLaren, C. M. Santori, R. S. Schreiber, S. M. Spillane, D. Vantrease, and Q. Xu, Applied Physics A., Vol. 95, No. 4, 2009
- "How to Simulate 1,000 Cores," M. Monchiero, J. Ahn, A. Falcon, D. Ortega, and P. Faraboschi,, in Workshop on Design, Architecture, and Simulation of Chip Multi-Processors, 2008
- "Corona: System Implications of Emerging Nanophotonic Technology," D. Vantrease, R. S. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. Beausoleil, and J. Ahn, in Proceedings of the 35th International Symposium on Computer Architecture, 2008
- "A Comprehensive Memory Modeling Tool and its Application to the Design and Analysis of Future Memory Hierarchies," S. Thoziyoor, J. Ahn, M. Monchiero, J. B. Brockman, and N. P. Jouppi, in Proceedings of the 35th International Symposium on Computer Architecture, 2008
- "Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs," J. Ahn, J. Leverich, R. S. Schreiber, and N. P. Jouppi, Computer Architecture Letters, Vol.8, No. 1, 2008
- "A Nanophotonic Interconnect for High-Performance Many-Core Computation," R. Beausoleil, J. Ahn, N. Binkert, A. Davis, D. Fattal, M. Fiorentino, N. P. Jouppi, M. McLaren, C. M. Santori, S. M. Spillane, D. Vantrease, and Q. Xu, in Integrated Photonics and Nanophotonics Research and Applications, 2008
- "CACTI 5.1," S. Thoziyoor, N. Muralimanohar, J. Ahn, and N. P. Jouppi,, Technical Report HPL-2008-20, 2008
- "Tradeoff between Data-, Instruction-, and Thread-Level Parallelism in Stream Processors," J. Ahn, M. Erez, and W. J. Dally, in Proceedings of the 21st International Conference on Supercomputing, 2007
- "Executing Irregular Scientific Applications on Stream Architectures," M. Erez, J. Ahn, J. Gummaraju, M. Rosenblum, and W. J. Dally, in Proceedings of the 21st annual international conference on Supercomputing, 2007
- "The Design Space of Data-Parallel Memory Systems," J. Ahn, M. Erez, and W. J. Dally, in Proceedings of the 2006 ACM/IEEE Conference on Supercomputing, 2006
- "Scatter-Add in Data Parallel Architectures," J. Ahn, M. Erez, and W. J. Dally, in Proceedings of the 11th International Symposium on High-Performance Computer Architecture, 2005
- "Data Parallel Address Architecture," J. Ahn and W. J. Dally, Computer Architecture Letters, Vol. 5, No. 1, 2005
- "Analysis and Performance Results of a Molecular Modeling Application on Merrimac," M. Erez, J. Ahn, A. Garg, W. J. Dally, and E. Darve, in Proceedings of the 2004 ACM/IEEE Conference on Supercomputing, 2004
- "Evaluating the Imagine stream architecture," J. Ahn, W. J. Dally, B. Khailany, U. Kapasi, and A. Das, in Proceedings 31st Annual International Symposium on Computer Architecture, 2004
- "Stream Register Files with Indexed Access," N. Jayasena, M. Erez, J. Ahn, and W. J. Dally, in Proceedings of the 10th International Symposium on High Performance Computer Architecture, 2004
- "Stream Processors: Programmability with Efficiency," W. J. Dally, U. Kapasi, B. Khailany, J. Ahn, and A. Das, ACM Queue, Vol. 2, No. 1, 2004
- "Merrimac: Supercomputing with Streams," W. J. Dally, P. Hanrahan, M. Erez, T. Knight, F. Labonte, J. Ahn, N. Jayasena, U. Kapasi, A. Das, J. Gummaraju, and I. Buck, in Proceedings of the 2003 ACM/IEEE Conference on Supercomputing, 2003
- "Programmable Stream Processors," U. Kapasi, S. Rixner, W. J. Dally, B. Khailany, J. Ahn, P. Mattson, and J. D. Owens, IEEE Computer, Vol. 36, No. 8, 2003